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32x: implement standard/ssf2 mapper
[picodrive.git] / pico / pico_int.h
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cff531af 1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
cc68a136 9\r
eff55556 10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
cc68a136 12\r
13#include <stdio.h>\r
cc68a136 14#include <string.h>\r
bce14421 15#include "pico_port.h"\r
efcba75f 16#include "pico.h"\r
f53f286a 17#include "carthw/carthw.h"\r
cc68a136 18\r
89fa852d 19//\r
20#define USE_POLL_DETECT\r
21\r
eff55556 22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
cc68a136 28\r
70357ce5 29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
d4d62665 38#include "../cpu/cyclone/Cyclone.h"\r
3aa1e148 39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
ae214f1c 40#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
41#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
3aa1e148 42#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
43#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
12da51c2 44#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
45#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
5fadfb1c 46#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
12da51c2 47#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
3aa1e148 48#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
49#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ed4402a7 50#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
ca61ee42 51#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
08769494 52#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 53\r
ecc8036e 54#define SekNotPolling PicoCpuCM68k.not_pol\r
55#define SekNotPollingS68k PicoCpuCS68k.not_pol\r
56\r
b542be46 57#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
5fadfb1c 58#define SekIrqLevel PicoCpuCM68k.irq\r
b542be46 59\r
cc68a136 60#endif\r
61\r
70357ce5 62#ifdef EMU_F68K\r
63#include "../cpu/fame/fame.h"\r
b542be46 64extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
ae214f1c 65#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
66#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
03e4f2a3 67#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
68#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
12da51c2 69#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
70#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
5fadfb1c 71#define SekSr PicoCpuFM68k.sr\r
12da51c2 72#define SekSrS68k PicoCpuFS68k.sr\r
70357ce5 73#define SekSetStop(x) { \\r
03e4f2a3 74 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
75 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 76}\r
77#define SekSetStopS68k(x) { \\r
03e4f2a3 78 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
79 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 80}\r
ed4402a7 81#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
ca61ee42 82#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
12f23dac 83#define SekShouldInterrupt() fm68k_would_interrupt(&PicoCpuFM68k)\r
b542be46 84\r
ecc8036e 85#define SekNotPolling PicoCpuFM68k.not_polling\r
86#define SekNotPollingS68k PicoCpuFS68k.not_polling\r
87\r
b542be46 88#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
5fadfb1c 89#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
b542be46 90\r
cc68a136 91#endif\r
92\r
93#ifdef EMU_M68K\r
94#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 95extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 96#ifndef SekCyclesLeft\r
ae214f1c 97#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
98#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
3aa1e148 99#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
100#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
12da51c2 101#define SekDar(x) PicoCpuMM68k.dar[x]\r
102#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
103#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
104#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
7a1f6e45 105#define SekSetStop(x) { \\r
3aa1e148 106 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
107 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 108}\r
109#define SekSetStopS68k(x) { \\r
3aa1e148 110 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
111 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 112}\r
ed4402a7 113#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
ca61ee42 114#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
08769494 115#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 116\r
ecc8036e 117#define SekNotPolling PicoCpuMM68k.not_polling\r
118#define SekNotPollingS68k PicoCpuMS68k.not_polling\r
119\r
22814963 120// avoid m68k_set_irq() for delaying to work\r
121#define SekInterrupt(irq) PicoCpuMM68k.int_level = (irq) << 8\r
122#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
b542be46 123\r
cc68a136 124#endif\r
ef090115 125#endif // EMU_M68K\r
cc68a136 126\r
ae214f1c 127// number of cycles done (can be checked anywhere)\r
88fd63ad 128#define SekCyclesDone() (Pico.t.m68c_cnt - SekCyclesLeft)\r
ae214f1c 129\r
130// burn cycles while not in SekRun() and while in\r
88fd63ad 131#define SekCyclesBurn(c) Pico.t.m68c_cnt += c\r
bc3c13d3 132#define SekCyclesBurnRun(c) { \\r
133 SekCyclesLeft -= c; \\r
b8cbd802 134}\r
cc68a136 135\r
ae214f1c 136// note: sometimes may extend timeslice to delay an irq\r
cc68a136 137#define SekEndRun(after) { \\r
88fd63ad 138 Pico.t.m68c_cnt -= SekCyclesLeft - (after); \\r
ae214f1c 139 SekCyclesLeft = after; \\r
cc68a136 140}\r
141\r
ae214f1c 142extern unsigned int SekCycleCntS68k;\r
143extern unsigned int SekCycleAimS68k;\r
144\r
07ceafdb 145#define SekEndRunS68k(after) { \\r
ae214f1c 146 if (SekCyclesLeftS68k > (after)) { \\r
147 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
148 SekCyclesLeftS68k = after; \\r
149 } \\r
07ceafdb 150}\r
151\r
ae214f1c 152#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
cc68a136 153\r
ae214f1c 154// compare cycles, handling overflows\r
155// check if a > b\r
156#define CYCLES_GT(a, b) \\r
157 ((int)((a) - (b)) > 0)\r
158// check if a >= b\r
159#define CYCLES_GE(a, b) \\r
160 ((int)((a) - (b)) >= 0)\r
cc68a136 161\r
b542be46 162// ----------------------- Z80 CPU -----------------------\r
163\r
b4db550e 164#if defined(_USE_DRZ80)\r
dca310c4 165#include "../cpu/DrZ80/drz80.h"\r
b542be46 166\r
167extern struct DrZ80 drZ80;\r
168\r
169#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
170#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
4936aac1 171#define z80_int() drZ80.Z80_IRQ = 1\r
835122bc 172#define z80_int() drZ80.Z80_IRQ = 1\r
173#define z80_nmi() drZ80.Z80IF |= 8\r
4b9c5888 174\r
175#define z80_cyclesLeft drZ80.cycles\r
d1b8bcc6 176#define z80_subCLeft(c) drZ80.cycles -= c\r
19954be1 177#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
b542be46 178\r
179#elif defined(_USE_CZ80)\r
dca310c4 180#include "../cpu/cz80/cz80.h"\r
b542be46 181\r
182#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
183#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
184#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
835122bc 185#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)\r
4b9c5888 186\r
187#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
d1b8bcc6 188#define z80_subCLeft(c) CZ80.ICount -= c\r
19954be1 189#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
b542be46 190\r
191#else\r
192\r
193#define z80_run(cycles) (cycles)\r
194#define z80_run_nr(cycles)\r
195#define z80_int()\r
835122bc 196#define z80_nmi()\r
b542be46 197\r
198#endif\r
199\r
b4db550e 200#define Z80_STATE_SIZE 0x60\r
201\r
4b9c5888 202#define z80_resetCycles() \\r
88fd63ad 203 Pico.t.z80c_cnt = Pico.t.z80c_aim = Pico.t.z80_scanline = 0\r
4b9c5888 204\r
205#define z80_cyclesDone() \\r
88fd63ad 206 (Pico.t.z80c_aim - z80_cyclesLeft)\r
4b9c5888 207\r
3162a710 208#define cycles_68k_to_z80(x) ((x) * 3823 >> 13)\r
4b9c5888 209\r
acd35d4c 210// ----------------------- SH2 CPU -----------------------\r
211\r
41397701 212#include "cpu/sh2/sh2.h"\r
acd35d4c 213\r
1d7a28a7 214extern SH2 sh2s[2];\r
215#define msh2 sh2s[0]\r
216#define ssh2 sh2s[1]\r
217\r
679af8a3 218#ifndef DRC_SH2\r
19886062 219# define sh2_end_run(sh2, after_) do { \\r
220 if ((sh2)->icount > (after_)) { \\r
c1931173 221 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
19886062 222 (sh2)->icount = after_; \\r
a8fd6e37 223 } \\r
224} while (0)\r
19886062 225# define sh2_cycles_left(sh2) (sh2)->icount\r
8a847c12 226# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
f81107f5 227# define sh2_pc(sh2) (sh2)->ppc\r
679af8a3 228#else\r
19886062 229# define sh2_end_run(sh2, after_) do { \\r
230 int left_ = (signed int)(sh2)->sr >> 12; \\r
231 if (left_ > (after_)) { \\r
c1931173 232 (sh2)->cycles_timeslice -= left_ - (after_); \\r
f4c0720c 233 (sh2)->sr &= 0xfff; \\r
19886062 234 (sh2)->sr |= (after_) << 12; \\r
a8fd6e37 235 } \\r
236} while (0)\r
19886062 237# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
8a847c12 238# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
f81107f5 239# define sh2_pc(sh2) (sh2)->pc\r
679af8a3 240#endif\r
266c6afa 241\r
19886062 242#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
a7f82a77 243#define sh2_cycles_done_t(sh2) \\r
244 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
19886062 245#define sh2_cycles_done_m68k(sh2) \\r
246 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
247\r
4ea707e1 248#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
249#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
250#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
6add7875 251#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
acd35d4c 252\r
83ff19ec 253#define sh2_set_gbr(c, v) \\r
254 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
255#define sh2_set_vbr(c, v) \\r
256 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
257\r
f8675e28 258#define elprintf_sh2(sh2, w, f, ...) \\r
259 elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
260\r
cc68a136 261// ---------------------------------------------------------\r
262\r
263// main oscillator clock which controls timing\r
264#define OSC_NTSC 53693100\r
b8cbd802 265#define OSC_PAL 53203424\r
cc68a136 266\r
e42a47e2 267// PicoVideo.debug_p\r
e0bcb7a9 268#define PVD_KILL_A (1 << 0)\r
269#define PVD_KILL_B (1 << 1)\r
270#define PVD_KILL_S_LO (1 << 2)\r
271#define PVD_KILL_S_HI (1 << 3)\r
272#define PVD_KILL_32X (1 << 4)\r
273#define PVD_FORCE_A (1 << 5)\r
274#define PVD_FORCE_B (1 << 6)\r
275#define PVD_FORCE_S (1 << 7)\r
276\r
e42a47e2 277// PicoVideo.status, not part of real SR\r
278#define SR_PAL (1 << 0)\r
279#define SR_DMA (1 << 1)\r
280#define SR_HB (1 << 2)\r
281#define SR_VB (1 << 3)\r
282#define SR_ODD (1 << 4)\r
283#define SR_C (1 << 5)\r
284#define SR_SOVR (1 << 6)\r
285#define SR_F (1 << 7)\r
286#define SR_FULL (1 << 8)\r
287#define SR_EMPT (1 << 9)\r
288// not part of real SR\r
289#define PVS_ACTIVE (1 << 16)\r
0e4bde9b 290#define PVS_VB2 (1 << 17) // ignores forced blanking\r
e42a47e2 291\r
cc68a136 292struct PicoVideo\r
293{\r
294 unsigned char reg[0x20];\r
b8cbd802 295 unsigned int command; // 32-bit Command\r
296 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
297 unsigned char type; // Command type (v/c/vsram read/write)\r
298 unsigned short addr; // Read/Write address\r
e42a47e2 299 unsigned int status; // Status bits (SR) and extra flags\r
cc68a136 300 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 301 signed char lwrite_cnt; // VDP write count during active display line\r
9761a7d0 302 unsigned short v_counter; // V-counter\r
e0bcb7a9 303 unsigned short debug; // raw debug register\r
304 unsigned char debug_p; // ... parsed: PVD_*\r
e42a47e2 305 unsigned char addr_u; // bit16 of .addr\r
306 unsigned char hint_cnt;\r
307 unsigned char pad[0x0b];\r
cc68a136 308};\r
309\r
310struct PicoMisc\r
311{\r
312 unsigned char rotate;\r
313 unsigned char z80Run;\r
e5503e2f 314 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
2aa27095 315 unsigned short scanline; // 04 0 to 261||311\r
e5503e2f 316 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
317 unsigned char hardware; // 07 Hardware value for country\r
318 unsigned char pal; // 08 1=PAL 0=NTSC\r
45f2f245 319 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
e5503e2f 320 unsigned short z80_bank68k; // 0a\r
be2c4208 321 unsigned short pad0;\r
fa8fb754 322 unsigned char ncart_in; // 0e !cart_in\r
0ace9b9a 323 unsigned char z80_reset; // 0f z80 reset held\r
e5503e2f 324 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 325 unsigned short eeprom_addr; // EEPROM address register\r
45f2f245 326 unsigned char eeprom_cycle; // EEPROM cycle number\r
1dceadae 327 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
45f2f245 328 unsigned char eeprom_status;\r
93f9619e 329 unsigned char status; // rapid_ym2612, multi_ym_updates\r
053fd9b4 330 unsigned short dma_xfers; // 18\r
45f2f245 331 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
053fd9b4 332 unsigned int frame_count; // 1c for movies and idle det\r
cc68a136 333};\r
334\r
b4db550e 335struct PicoMS\r
336{\r
337 unsigned char carthw[0x10];\r
338 unsigned char io_ctl;\r
835122bc 339 unsigned char nmi_state;\r
340 unsigned char pad[0x4e];\r
b4db550e 341};\r
342\r
ea38612f 343// emu state and data for the asm code\r
344struct PicoEState\r
345{\r
346 int DrawScanline;\r
347 int rendstatus;\r
98a27142 348 void *DrawLineDest; // draw destination\r
99bdfd31 349 unsigned char *HighCol;\r
350 int *HighPreSpr;\r
88fd63ad 351 struct Pico *Pico;\r
352 void *PicoMem_vram;\r
353 void *PicoMem_cram;\r
93f9619e 354 unsigned int *PicoOpt;\r
98a27142 355 unsigned char *Draw2FB;\r
356 unsigned short HighPal[0x100];\r
ea38612f 357};\r
358\r
88fd63ad 359struct PicoMem\r
cc68a136 360{\r
361 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
200772b7 362 union { // vram is byteswapped for easier reads when drawing\r
2ec9bec5 363 unsigned short vram[0x8000]; // 0x10000\r
364 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
365 };\r
cc68a136 366 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
b4db550e 367 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
cf07a88d 368 unsigned short cram[0x40]; // 0x22010\r
369 unsigned char pad[0x70]; // 0x22050 DrawStripVSRam reads 0 from here\r
370 unsigned short vsram[0x40]; // 0x22100\r
cc68a136 371};\r
372\r
373// sram\r
45f2f245 374#define SRR_MAPPED (1 << 0)\r
375#define SRR_READONLY (1 << 1)\r
376\r
377#define SRF_ENABLED (1 << 0)\r
378#define SRF_EEPROM (1 << 1)\r
af37bca8 379\r
88fd63ad 380struct PicoCartSave\r
cc68a136 381{\r
4ff2d527 382 unsigned char *data; // actual data\r
383 unsigned int start; // start address in 68k address space\r
cc68a136 384 unsigned int end;\r
45f2f245 385 unsigned char flags; // 0c: SRF_*\r
1dceadae 386 unsigned char unused2;\r
cc68a136 387 unsigned char changed;\r
45f2f245 388 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
389 unsigned char unused3;\r
1dceadae 390 unsigned char eeprom_bit_cl; // bit number for cl\r
391 unsigned char eeprom_bit_in; // bit number for in\r
392 unsigned char eeprom_bit_out; // bit number for out\r
45f2f245 393 unsigned int size;\r
cc68a136 394};\r
395\r
88fd63ad 396struct PicoTiming\r
397{\r
398 // while running, cnt represents target of current timeslice\r
399 // while not in SekRun(), it's actual cycles done\r
400 // (but always use SekCyclesDone() if you need current position)\r
401 // _cnt may change if timeslice is ended prematurely or extended,\r
402 // so we use _aim for the actual target\r
403 unsigned int m68c_cnt;\r
404 unsigned int m68c_aim;\r
405 unsigned int m68c_frame_start; // m68k cycles\r
406 unsigned int m68c_line_start;\r
407\r
408 unsigned int z80c_cnt; // z80 cycles done (this frame)\r
409 unsigned int z80c_aim;\r
410 int z80_scanline;\r
6311a3ba 411\r
412 int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
413 int timer_b_next_oflow, timer_b_step;\r
414};\r
415\r
416struct PicoSound\r
417{\r
418 short len; // number of mono samples\r
419 short len_use; // adjusted\r
420 int len_e_add; // for non-int samples/frame\r
421 int len_e_cnt;\r
422 short dac_line;\r
423 short psg_line;\r
88fd63ad 424};\r
425\r
426// run tools/mkoffsets pico/pico_int_o32.h if you change these\r
427// careful with savestate compat\r
428struct Pico\r
429{\r
430 struct PicoVideo video;\r
431 struct PicoMisc m;\r
432 struct PicoTiming t;\r
433 struct PicoCartSave sv;\r
6311a3ba 434 struct PicoSound snd;\r
88fd63ad 435 struct PicoEState est;\r
436 struct PicoMS ms;\r
437\r
438 unsigned char *rom;\r
439 unsigned int romsize;\r
440};\r
441\r
cc68a136 442// MCD\r
33be04ca 443#define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)\r
444\r
4f265db7 445struct mcd_pcm\r
446{\r
447 unsigned char control; // reg7\r
448 unsigned char enabled; // reg8\r
449 unsigned char cur_ch;\r
450 unsigned char bank;\r
33be04ca 451 unsigned int update_cycles;\r
4f265db7 452\r
4ff2d527 453 struct pcm_chan // 08, size 0x10\r
4f265db7 454 {\r
455 unsigned char regs[8];\r
4ff2d527 456 unsigned int addr; // .08: played sample address\r
4f265db7 457 int pad;\r
458 } ch[8];\r
459};\r
460\r
4fb43555 461#define PCD_ST_S68K_RST 1\r
462\r
c459aefd 463struct mcd_misc\r
464{\r
6901d0e4 465 unsigned short hint_vector;\r
466 unsigned char busreq; // not s68k_regs[1]\r
467 unsigned char s68k_pend_ints;\r
468 unsigned int state_flags; // 04\r
469 unsigned int stopwatch_base_c;\r
470 unsigned short m68k_poll_a;\r
471 unsigned short m68k_poll_cnt;\r
472 unsigned short s68k_poll_a;\r
473 unsigned short s68k_poll_cnt;\r
474 unsigned int s68k_poll_clk;\r
475 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
476 unsigned char dmna_ret_2m;\r
477 unsigned char need_sync;\r
478 unsigned char pad3;\r
479 int pad4[9];\r
c459aefd 480};\r
481\r
cc68a136 482typedef struct\r
483{\r
3f23709e 484 unsigned char bios[0x20000]; // 000000: 128K\r
485 union { // 020000: 512K\r
486 unsigned char prg_ram[0x80000];\r
487 unsigned char prg_ram_b[4][0x20000];\r
488 };\r
489 union { // 0a0000: 256K\r
490 struct {\r
491 unsigned char word_ram2M[0x40000];\r
492 unsigned char unused0[0x20000];\r
493 };\r
494 struct {\r
495 unsigned char unused1[0x20000];\r
496 unsigned char word_ram1M[2][0x20000];\r
497 };\r
498 };\r
499 union { // 100000: 64K\r
500 unsigned char pcm_ram[0x10000];\r
501 unsigned char pcm_ram_b[0x10][0x1000];\r
502 };\r
f47d0a28 503 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
3f23709e 504 unsigned char bram[0x2000]; // 110200: 8K\r
505 struct mcd_misc m; // 112200: misc\r
506 struct mcd_pcm pcm; // 112240:\r
274fcc35 507 void *cdda_stream;\r
508 int cdda_type;\r
3f23709e 509 int pcm_mixbuf[PCM_MIXBUF_LEN * 2];\r
510 int pcm_mixpos;\r
511 char pcm_mixbuf_dirty;\r
512 char pcm_regs_dirty;\r
cc68a136 513} mcd_state;\r
514\r
be2c4208 515// XXX: this will need to be reworked for cart+cd support.\r
cc68a136 516#define Pico_mcd ((mcd_state *)Pico.rom)\r
517\r
be2c4208 518// 32X\r
acd35d4c 519#define P32XS_FM (1<<15)\r
fa8fb754 520#define P32XS_nCART (1<< 8)\r
83ff19ec 521#define P32XS_REN (1<< 7)\r
522#define P32XS_nRES (1<< 1)\r
523#define P32XS_ADEN (1<< 0)\r
acd35d4c 524#define P32XS2_ADEN (1<< 9)\r
5e128c6d 525#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
4ea707e1 526#define P32XS_68S (1<< 2)\r
97d3f47f 527#define P32XS_DMA (1<< 1)\r
4ea707e1 528#define P32XS_RV (1<< 0)\r
acd35d4c 529\r
5e128c6d 530#define P32XV_nPAL (1<<15) // VDP\r
acd35d4c 531#define P32XV_PRI (1<< 7)\r
4ea707e1 532#define P32XV_Mx (3<< 0) // display mode mask\r
974fdb5b 533\r
e51e5983 534#define P32XV_SFT (1<< 0)\r
535\r
acd35d4c 536#define P32XV_VBLK (1<<15)\r
537#define P32XV_HBLK (1<<14)\r
538#define P32XV_PEN (1<<13)\r
539#define P32XV_nFEN (1<< 1)\r
540#define P32XV_FS (1<< 0)\r
974fdb5b 541\r
df63f1a6 542#define P32XP_RTP (1<<7) // PWM control\r
543#define P32XP_FULL (1<<15) // PWM pulse\r
db1d3564 544#define P32XP_EMPTY (1<<14)\r
545\r
419973a6 546#define P32XF_68KCPOLL (1 << 0)\r
547#define P32XF_68KVPOLL (1 << 1)\r
548#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
8b9dbcde 549#define P32XF_DRC_ROM_C (1 << 8) // cached code from ROM\r
4ea707e1 550\r
551#define P32XI_VRES (1 << 14/2) // IRL/2\r
552#define P32XI_VINT (1 << 12/2)\r
553#define P32XI_HINT (1 << 10/2)\r
554#define P32XI_CMD (1 << 8/2)\r
555#define P32XI_PWM (1 << 6/2)\r
556\r
1d7a28a7 557// peripheral reg access\r
558#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
559\r
7eaa3812 560#define DMAC_FIFO_LEN (4*2)\r
db1d3564 561#define PWM_BUFF_LEN 1024 // in one channel samples\r
266c6afa 562\r
f4bb5d6b 563#define SH2_DRCBLK_RAM_SHIFT 1\r
564#define SH2_DRCBLK_DA_SHIFT 1\r
565\r
f81107f5 566#define SH2_READ_SHIFT 25\r
e05b81fc 567#define SH2_WRITE_SHIFT 25\r
568\r
be2c4208 569struct Pico32x\r
570{\r
571 unsigned short regs[0x20];\r
5a681086 572 unsigned short vdp_regs[0x10]; // 0x40\r
573 unsigned short sh2_regs[3]; // 0x60\r
be2c4208 574 unsigned char pending_fb;\r
974fdb5b 575 unsigned char dirty_pal;\r
266c6afa 576 unsigned int emu_flags;\r
4ea707e1 577 unsigned char sh2irq_mask[2];\r
578 unsigned char sh2irqi[2]; // individual\r
579 unsigned int sh2irqs; // common irqs\r
580 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
7eaa3812 581 unsigned int pad[4];\r
df63f1a6 582 unsigned int dmac0_fifo_ptr;\r
4a1fb183 583 unsigned short vdp_fbcr_fake;\r
7eaa3812 584 unsigned short pad2;\r
31fbc691 585 unsigned char comm_dirty;\r
586 unsigned char pad3; // was comm_dirty_sh2\r
df63f1a6 587 unsigned char pwm_irq_cnt;\r
588 unsigned char pad1;\r
a7f82a77 589 unsigned short pwm_p[2]; // pwm pos in fifo\r
590 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
591 unsigned int reserved[6];\r
974fdb5b 592};\r
593\r
594struct Pico32xMem\r
595{\r
596 unsigned char sdram[0x40000];\r
f4bb5d6b 597#ifdef DRC_SH2\r
598 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
599#endif\r
b78efee2 600 unsigned short dram[2][0x20000/2]; // AKA fb\r
b4db550e 601 union {\r
602 unsigned char m68k_rom[0x100];\r
603 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
604 };\r
f4bb5d6b 605#ifdef DRC_SH2\r
606 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
607#endif\r
895d1512 608 union {\r
609 unsigned char b[0x800];\r
610 unsigned short w[0x800/2];\r
611 } sh2_rom_m;\r
612 union {\r
613 unsigned char b[0x400];\r
614 unsigned short w[0x400/2];\r
615 } sh2_rom_s;\r
974fdb5b 616 unsigned short pal[0x100];\r
5e128c6d 617 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
db1d3564 618 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
8ce9c3a7 619 signed short pwm_current[2]; // current converted samples\r
620 unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
be2c4208 621};\r
d49b10c2 622\r
c8d1e9b6 623// area.c\r
fad24893 624extern void (*PicoLoadStateHook)(void);\r
51a902ae 625\r
945c2fdc 626typedef struct {\r
627 int chunk;\r
628 int size;\r
629 void *ptr;\r
630} carthw_state_chunk;\r
631extern carthw_state_chunk *carthw_chunks;\r
632#define CHUNK_CARTHW 64\r
633\r
c8d1e9b6 634// cart.c\r
b4db550e 635extern int PicoCartResize(int newsize);\r
636extern void Byteswap(void *dst, const void *src, int len);\r
45f2f245 637extern void (*PicoCartMemSetup)(void);\r
e807ac75 638extern void (*PicoCartUnloadHook)(void);\r
1dceadae 639\r
c8d1e9b6 640// debug.c\r
b5e5172d 641int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 642\r
c8d1e9b6 643// draw.c\r
99bdfd31 644void PicoDrawInit(void);\r
eff55556 645PICO_INTERNAL void PicoFrameStart(void);\r
b6d7ac70 646void PicoDrawSync(int to, int blank_last_line);\r
99bdfd31 647void BackFill(int reg7, int sh, struct PicoEState *est);\r
ea38612f 648void FinalizeLine555(int sh, int line, struct PicoEState *est);\r
f4750ee0 649extern int (*PicoScanBegin)(unsigned int num);\r
650extern int (*PicoScanEnd)(unsigned int num);\r
f579f7b8 651#define MAX_LINE_SPRITES 29\r
652extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
5a681086 653extern void *DrawLineDestBase;\r
654extern int DrawLineDestIncrement;\r
cc68a136 655\r
c8d1e9b6 656// draw2.c\r
98a27142 657void PicoDraw2Init(void);\r
eff55556 658PICO_INTERNAL void PicoFrameFull();\r
cc68a136 659\r
200772b7 660// mode4.c\r
661void PicoFrameStartMode4(void);\r
662void PicoLineMode4(int line);\r
663void PicoDoHighPal555M4(void);\r
5a681086 664void PicoDrawSetOutputMode4(pdso_t which);\r
200772b7 665\r
c8d1e9b6 666// memory.c\r
eff55556 667PICO_INTERNAL void PicoMemSetup(void);\r
af37bca8 668unsigned int PicoRead8_io(unsigned int a);\r
669unsigned int PicoRead16_io(unsigned int a);\r
670void PicoWrite8_io(unsigned int a, unsigned int d);\r
671void PicoWrite16_io(unsigned int a, unsigned int d);\r
672\r
673// pico/memory.c\r
674PICO_INTERNAL void PicoMemSetupPico(void);\r
cc68a136 675\r
3f23709e 676// cd/cdc.c\r
677void cdc_init(void);\r
678void cdc_reset(void);\r
679int cdc_context_save(unsigned char *state);\r
680int cdc_context_load(unsigned char *state);\r
681int cdc_context_load_old(unsigned char *state);\r
682void cdc_dma_update(void);\r
683int cdc_decoder_update(unsigned char header[4]);\r
684void cdc_reg_w(unsigned char data);\r
685unsigned char cdc_reg_r(void);\r
686unsigned short cdc_host_r(void);\r
687\r
274fcc35 688// cd/cdd.c\r
689void cdd_reset(void);\r
690int cdd_context_save(unsigned char *state);\r
691int cdd_context_load(unsigned char *state);\r
692int cdd_context_load_old(unsigned char *state);\r
693void cdd_read_data(unsigned char *dst);\r
694void cdd_read_audio(unsigned int samples);\r
695void cdd_update(void);\r
696void cdd_process(void);\r
697\r
698// cd/cd_image.c\r
699int load_cd_image(const char *cd_img_name, int *type);\r
700\r
a93a80de 701// cd/gfx.c\r
702void gfx_init(void);\r
703void gfx_start(unsigned int base);\r
704void gfx_update(unsigned int cycles);\r
705int gfx_context_save(unsigned char *state);\r
706int gfx_context_load(const unsigned char *state);\r
707\r
708// cd/gfx_dma.c\r
709void DmaSlowCell(unsigned int source, unsigned int a, int len, unsigned char inc);\r
710\r
c8d1e9b6 711// cd/memory.c\r
eff55556 712PICO_INTERNAL void PicoMemSetupCD(void);\r
fa8fb754 713unsigned int PicoRead8_mcd_io(unsigned int a);\r
714unsigned int PicoRead16_mcd_io(unsigned int a);\r
715void PicoWrite8_mcd_io(unsigned int a, unsigned int d);\r
716void PicoWrite16_mcd_io(unsigned int a, unsigned int d);\r
ae214f1c 717void pcd_state_loaded_mem(void);\r
cc68a136 718\r
c8d1e9b6 719// pico.c\r
cc68a136 720extern struct Pico Pico;\r
88fd63ad 721extern struct PicoMem PicoMem;\r
f8ef8ff7 722extern void (*PicoResetHook)(void);\r
b0677887 723extern void (*PicoLineHook)(void);\r
1e6b5e39 724PICO_INTERNAL int CheckDMA(void);\r
725PICO_INTERNAL void PicoDetectRegion(void);\r
ae214f1c 726PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
cc68a136 727\r
89dbbf2b 728// cd/mcd.c\r
ae214f1c 729#define PCDS_IEN1 (1<<1)\r
730#define PCDS_IEN2 (1<<2)\r
731#define PCDS_IEN3 (1<<3)\r
732#define PCDS_IEN4 (1<<4)\r
733#define PCDS_IEN5 (1<<5)\r
734#define PCDS_IEN6 (1<<6)\r
cc68a136 735\r
2aa27095 736PICO_INTERNAL void PicoInitMCD(void);\r
e5f426aa 737PICO_INTERNAL void PicoExitMCD(void);\r
1cb1584b 738PICO_INTERNAL void PicoPowerMCD(void);\r
2aa27095 739PICO_INTERNAL int PicoResetMCD(void);\r
740PICO_INTERNAL void PicoFrameMCD(void);\r
cc68a136 741\r
ae214f1c 742enum pcd_event {\r
743 PCD_EVENT_CDC,\r
744 PCD_EVENT_TIMER3,\r
745 PCD_EVENT_GFX,\r
746 PCD_EVENT_DMA,\r
747 PCD_EVENT_COUNT,\r
748};\r
749extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
750void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
751void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
a6523294 752void pcd_prepare_frame(void);\r
ae214f1c 753unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
08769494 754int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
fa8fb754 755void pcd_run_cpus(int m68k_cycles);\r
d0132772 756void pcd_soft_reset(void);\r
ae214f1c 757void pcd_state_loaded(void);\r
758\r
33be04ca 759// cd/pcm.c\r
760void pcd_pcm_sync(unsigned int to);\r
761void pcd_pcm_update(int *buffer, int length, int stereo);\r
762void pcd_pcm_write(unsigned int a, unsigned int d);\r
763unsigned int pcd_pcm_read(unsigned int a);\r
764\r
c8d1e9b6 765// pico/pico.c\r
2aa27095 766PICO_INTERNAL void PicoInitPico(void);\r
ed367a3f 767PICO_INTERNAL void PicoReratePico(void);\r
9037e45d 768\r
c8d1e9b6 769// pico/xpcm.c\r
ef4eb506 770PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
771PICO_INTERNAL void PicoPicoPCMReset(void);\r
213c16ad 772PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
ef4eb506 773\r
c8d1e9b6 774// sek.c\r
2aa27095 775PICO_INTERNAL void SekInit(void);\r
776PICO_INTERNAL int SekReset(void);\r
3aa1e148 777PICO_INTERNAL void SekState(int *data);\r
eff55556 778PICO_INTERNAL void SekSetRealTAS(int use_real);\r
b4db550e 779PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
780PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
5f9a0d16 781void SekStepM68k(void);\r
053fd9b4 782void SekInitIdleDet(void);\r
783void SekFinishIdleDet(void);\r
12da51c2 784#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
785void SekTrace(int is_s68k);\r
786#else\r
787#define SekTrace(x)\r
788#endif\r
cc68a136 789\r
c8d1e9b6 790// cd/sek.c\r
2aa27095 791PICO_INTERNAL void SekInitS68k(void);\r
792PICO_INTERNAL int SekResetS68k(void);\r
793PICO_INTERNAL int SekInterruptS68k(int irq);\r
3f23709e 794void SekInterruptClearS68k(int irq);\r
cc68a136 795\r
7a93adeb 796// sound/sound.c\r
c9e1affc 797extern short cdda_out_buffer[2*1152];\r
43e6eaad 798\r
274fcc35 799void cdda_start_play(int lba_base, int lba_offset, int lb_len);\r
800\r
43e6eaad 801void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
d2721b08 802void ym2612_pack_state(void);\r
453d2a6e 803void ym2612_unpack_state(void);\r
4b9c5888 804\r
e53704e6 805#define TIMER_NO_OFLOW 0x70000000\r
45a1ef71 806// tA = 72 * (1024 - NA) / M\r
807#define TIMER_A_TICK_ZCYCLES 17203\r
808// tB = 1152 * (256 - NA) / M\r
809#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
e53704e6 810\r
4b9c5888 811#define timers_cycle() \\r
6311a3ba 812 if (Pico.t.timer_a_next_oflow > 0 && Pico.t.timer_a_next_oflow < TIMER_NO_OFLOW) \\r
813 Pico.t.timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
814 if (Pico.t.timer_b_next_oflow > 0 && Pico.t.timer_b_next_oflow < TIMER_NO_OFLOW) \\r
815 Pico.t.timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
43e6eaad 816 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
4b9c5888 817\r
818#define timers_reset() \\r
6311a3ba 819 Pico.t.timer_a_next_oflow = Pico.t.timer_b_next_oflow = TIMER_NO_OFLOW; \\r
820 Pico.t.timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
821 Pico.t.timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
43e6eaad 822\r
7a93adeb 823\r
c8d1e9b6 824// videoport.c\r
eff55556 825PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
826PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
75b84e4b 827unsigned char PicoVideoRead8DataH(void);\r
828unsigned char PicoVideoRead8DataL(void);\r
829unsigned char PicoVideoRead8CtlH(void);\r
830unsigned char PicoVideoRead8CtlL(void);\r
831unsigned char PicoVideoRead8HV_H(void);\r
832unsigned char PicoVideoRead8HV_L(void);\r
0c7d1ba3 833extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned int *mask);\r
cc68a136 834\r
c8d1e9b6 835// misc.c\r
eff55556 836PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
fbba0ff6 837PICO_INTERNAL_ASM void memset32(void *dest, int c, int count);\r
cc68a136 838\r
45f2f245 839// eeprom.c\r
840void EEPROM_write8(unsigned int a, unsigned int d);\r
841void EEPROM_write16(unsigned int d);\r
842unsigned int EEPROM_read(void);\r
843\r
c8d1e9b6 844// z80 functionality wrappers\r
845PICO_INTERNAL void z80_init(void);\r
b4db550e 846PICO_INTERNAL void z80_pack(void *data);\r
847PICO_INTERNAL int z80_unpack(const void *data);\r
c8d1e9b6 848PICO_INTERNAL void z80_reset(void);\r
849PICO_INTERNAL void z80_exit(void);\r
c8d1e9b6 850\r
851// cd/misc.c\r
eff55556 852PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
853PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
854\r
eff55556 855// sound/sound.c\r
9d917eea 856PICO_INTERNAL void PsndReset(void);\r
4f2cdbf5 857PICO_INTERNAL void PsndStartFrame(void);\r
4b9c5888 858PICO_INTERNAL void PsndDoDAC(int line_to);\r
5d638db0 859PICO_INTERNAL void PsndDoPSG(int line_to);\r
9d917eea 860PICO_INTERNAL void PsndClear(void);\r
7b3f44c6 861PICO_INTERNAL void PsndGetSamples(int y);\r
2ec9bec5 862PICO_INTERNAL void PsndGetSamplesMS(void);\r
cc68a136 863\r
3e49ffd0 864// sms.c\r
f3a57b2d 865#ifndef NO_SMS\r
3e49ffd0 866void PicoPowerMS(void);\r
2ec9bec5 867void PicoResetMS(void);\r
3e49ffd0 868void PicoMemSetupMS(void);\r
b4db550e 869void PicoStateLoadedMS(void);\r
3e49ffd0 870void PicoFrameMS(void);\r
87b0845f 871void PicoFrameDrawOnlyMS(void);\r
f3a57b2d 872#else\r
873#define PicoPowerMS()\r
874#define PicoResetMS()\r
875#define PicoMemSetupMS()\r
876#define PicoStateLoadedMS()\r
877#define PicoFrameMS()\r
878#define PicoFrameDrawOnlyMS()\r
879#endif\r
3e49ffd0 880\r
be2c4208 881// 32x/32x.c\r
f3a57b2d 882#ifndef NO_32X\r
be2c4208 883extern struct Pico32x Pico32x;\r
6a98f03e 884enum p32x_event {\r
885 P32X_EVENT_PWM,\r
886 P32X_EVENT_FILLEND,\r
5ac99d9a 887 P32X_EVENT_HINT,\r
6a98f03e 888 P32X_EVENT_COUNT,\r
889};\r
ae214f1c 890extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
6a98f03e 891\r
be2c4208 892void Pico32xInit(void);\r
974fdb5b 893void PicoPower32x(void);\r
be2c4208 894void PicoReset32x(void);\r
974fdb5b 895void Pico32xStartup(void);\r
5e49c3a8 896void PicoUnload32x(void);\r
974fdb5b 897void PicoFrame32x(void);\r
27e26273 898void Pico32xStateLoaded(int is_early);\r
ed4402a7 899void p32x_sync_sh2s(unsigned int m68k_target);\r
19886062 900void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
4d5dfee8 901void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
9e1fa0a6 902void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
903void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
83ff19ec 904void p32x_reset_sh2s(void);\r
19886062 905void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
906void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
5ac99d9a 907void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
a8fd6e37 908\r
be2c4208 909// 32x/memory.c\r
88fd63ad 910extern struct Pico32xMem *Pico32xMem;\r
be2c4208 911unsigned int PicoRead8_32x(unsigned int a);\r
912unsigned int PicoRead16_32x(unsigned int a);\r
913void PicoWrite8_32x(unsigned int a, unsigned int d);\r
914void PicoWrite16_32x(unsigned int a, unsigned int d);\r
915void PicoMemSetup32x(void);\r
974fdb5b 916void Pico32xSwapDRAM(int b);\r
27e26273 917void Pico32xMemStateLoaded(void);\r
8b9dbcde 918void p32x_update_banks(void);\r
19886062 919void p32x_m68k_poll_event(unsigned int flags);\r
920void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
974fdb5b 921\r
922// 32x/draw.c\r
41946d70 923void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
ea38612f 924void FinalizeLine32xRGB555(int sh, int line, struct PicoEState *est);\r
5a681086 925void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
7a961c19 926void PicoDraw32xLayerMdOnly(int offs, int lines);\r
f4750ee0 927extern int (*PicoScan32xBegin)(unsigned int num);\r
928extern int (*PicoScan32xEnd)(unsigned int num);\r
7a961c19 929enum {\r
930 PDM32X_OFF,\r
931 PDM32X_32X_ONLY,\r
932 PDM32X_BOTH,\r
933};\r
5a681086 934extern int Pico32xDrawMode;\r
be2c4208 935\r
db1d3564 936// 32x/pwm.c\r
c1931173 937unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
938 unsigned int m68k_cycles);\r
939void p32x_pwm_write16(unsigned int a, unsigned int d,\r
940 SH2 *sh2, unsigned int m68k_cycles);\r
db1d3564 941void p32x_pwm_update(int *buf32, int length, int stereo);\r
045a4c52 942void p32x_pwm_ctl_changed(void);\r
df63f1a6 943void p32x_pwm_schedule(unsigned int m68k_now);\r
19886062 944void p32x_pwm_schedule_sh2(SH2 *sh2);\r
9e1fa0a6 945void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
df63f1a6 946void p32x_pwm_irq_event(unsigned int m68k_now);\r
947void p32x_pwm_state_loaded(void);\r
045a4c52 948\r
949// 32x/sh2soc.c\r
950void p32x_dreq0_trigger(void);\r
951void p32x_dreq1_trigger(void);\r
952void p32x_timers_recalc(void);\r
953void p32x_timers_do(unsigned int m68k_slice);\r
cd0ace28 954void sh2_peripheral_reset(SH2 *sh2);\r
f81107f5 955unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
956unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
957unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
8b43bc73 958void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
959void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
960void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
045a4c52 961\r
f3a57b2d 962#else\r
963#define Pico32xInit()\r
964#define PicoPower32x()\r
965#define PicoReset32x()\r
966#define PicoFrame32x()\r
967#define PicoUnload32x()\r
968#define Pico32xStateLoaded()\r
f3a57b2d 969#define FinalizeLine32xRGB555 NULL\r
970#define p32x_pwm_update(...)\r
971#define p32x_timers_recalc()\r
972#endif\r
db1d3564 973\r
45f2f245 974/* avoid dependency on newer glibc */\r
975static __inline int isspace_(int c)\r
976{\r
977 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
978}\r
979\r
f4bb5d6b 980#ifndef ARRAY_SIZE\r
981#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
982#endif\r
983\r
b8cbd802 984// emulation event logging\r
985#ifndef EL_LOGMASK\r
9c9cda8c 986# ifdef __x86_64__ // HACK\r
91be5ebd 987# define EL_LOGMASK (EL_STATUS|EL_ANOMALY)\r
9c9cda8c 988# else\r
1555935b 989# define EL_LOGMASK (EL_STATUS)\r
9c9cda8c 990# endif\r
b8cbd802 991#endif\r
992\r
017512f2 993#define EL_HVCNT 0x00000001 /* hv counter reads */\r
994#define EL_SR 0x00000002 /* SR reads */\r
995#define EL_INTS 0x00000004 /* ints and acks */\r
43e6eaad 996#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
017512f2 997#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
998#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
999#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
1000#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
1001#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
1002#define EL_SRAMIO 0x00000200 /* sram i/o */\r
1003#define EL_EEPROM 0x00000400 /* eeprom debug */\r
1004#define EL_UIO 0x00000800 /* unmapped i/o */\r
1005#define EL_IO 0x00001000 /* all i/o */\r
1006#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
1007#define EL_SVP 0x00004000 /* SVP stuff */\r
fa22af4c 1008#define EL_PICOHW 0x00008000 /* Pico stuff */\r
053fd9b4 1009#define EL_IDLE 0x00010000 /* idle loop det. */\r
af37bca8 1010#define EL_CDREGS 0x00020000 /* MCD: register access */\r
1011#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
be2c4208 1012#define EL_32X 0x00080000\r
1b3f5844 1013#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
045a4c52 1014#define EL_32XP 0x00200000 /* 32X peripherals */\r
ae214f1c 1015#define EL_CD 0x00400000 /* MCD */\r
017512f2 1016\r
1017#define EL_STATUS 0x40000000 /* status messages */\r
1018#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802 1019\r
1020#if EL_LOGMASK\r
1021#define elprintf(w,f,...) \\r
a8fd6e37 1022do { \\r
b8cbd802 1023 if ((w) & EL_LOGMASK) \\r
7d0143a2 1024 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
a8fd6e37 1025} while (0)\r
dca310c4 1026#elif defined(_MSC_VER)\r
1027#define elprintf\r
b8cbd802 1028#else\r
1029#define elprintf(w,f,...)\r
1030#endif\r
1031\r
f6c49d38 1032// profiling\r
1033#ifdef PPROF\r
1034#include <platform/linux/pprof.h>\r
1035#else\r
1036#define pprof_init()\r
1037#define pprof_finish()\r
1038#define pprof_start(x)\r
1039#define pprof_end(...)\r
1040#define pprof_end_sub(...)\r
1041#endif\r
1042\r
19886062 1043#ifdef EVT_LOG\r
1044enum evt {\r
1045 EVT_FRAME_START,\r
1046 EVT_NEXT_LINE,\r
1047 EVT_RUN_START,\r
1048 EVT_RUN_END,\r
1049 EVT_POLL_START,\r
1050 EVT_POLL_END,\r
1051 EVT_CNT\r
1052};\r
1053\r
1054enum evt_cpu {\r
1055 EVT_M68K,\r
1056 EVT_S68K,\r
1057 EVT_MSH2,\r
1058 EVT_SSH2,\r
1059 EVT_CPU_CNT\r
1060};\r
1061\r
1062void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
1063void pevt_dump(void);\r
1064\r
1065#define pevt_log_m68k(e) \\r
08769494 1066 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
19886062 1067#define pevt_log_m68k_o(e) \\r
08769494 1068 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
19886062 1069#define pevt_log_sh2(sh2, e) \\r
1070 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
1071#define pevt_log_sh2_o(sh2, e) \\r
1072 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
1073#else\r
1074#define pevt_log(c, e)\r
1075#define pevt_log_m68k(e)\r
1076#define pevt_log_m68k_o(e)\r
1077#define pevt_log_sh2(sh2, e)\r
1078#define pevt_log_sh2_o(sh2, e)\r
1079#define pevt_dump()\r
1080#endif\r
1081\r
f8af9634 1082#ifdef __cplusplus\r
1083} // End of extern "C"\r
1084#endif\r
1085\r
eff55556 1086#endif // PICO_INTERNAL_INCLUDED\r
1087\r
3162a710 1088// vim:shiftwidth=2:ts=2:expandtab\r
fast MegaDrive/MegaCD/32X emulator