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fix android build
[picodrive.git] / pico / pico_int.h
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cff531af 1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
cc68a136 9\r
eff55556 10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
cc68a136 12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
efcba75f 16#include "pico.h"\r
f53f286a 17#include "carthw/carthw.h"\r
cc68a136 18\r
89fa852d 19//\r
20#define USE_POLL_DETECT\r
21\r
eff55556 22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
cc68a136 28\r
70357ce5 29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
cc68a136 30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
5e2c5b93
T		 35#ifdef _MSC_VER\r
36#define snprintf _snprintf\r
37#define strcasecmp _stricmp\r
38#define strncasecmp _strnicmp\r
39#endif\r
cc68a136 40\r
41// ----------------------- 68000 CPU -----------------------\r
42#ifdef EMU_C68K\r
d4d62665 43#include "../cpu/cyclone/Cyclone.h"\r
3aa1e148 44extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
ae214f1c 45#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
46#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
3aa1e148 47#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
48#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
12da51c2 49#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
50#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
5fadfb1c 51#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
12da51c2 52#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
3aa1e148 53#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
54#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
ed4402a7 55#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
ca61ee42 56#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
08769494 57#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
b542be46 58\r
ecc8036e 59#define SekNotPolling PicoCpuCM68k.not_pol\r
60#define SekNotPollingS68k PicoCpuCS68k.not_pol\r
61\r
b542be46 62#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
5fadfb1c 63#define SekIrqLevel PicoCpuCM68k.irq\r
b542be46 64\r
cc68a136 65#endif\r
66\r
70357ce5 67#ifdef EMU_F68K\r
68#include "../cpu/fame/fame.h"\r
b542be46 69extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
ae214f1c 70#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
71#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
03e4f2a3 72#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
73#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
12da51c2 74#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
75#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
5fadfb1c 76#define SekSr PicoCpuFM68k.sr\r
12da51c2 77#define SekSrS68k PicoCpuFS68k.sr\r
70357ce5 78#define SekSetStop(x) { \\r
03e4f2a3 79 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
80 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
70357ce5 81}\r
82#define SekSetStopS68k(x) { \\r
03e4f2a3 83 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
84 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
70357ce5 85}\r
ed4402a7 86#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
ca61ee42 87#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
08769494 88#define SekShouldInterrupt() fm68k_would_interrupt()\r
b542be46 89\r
ecc8036e 90#define SekNotPolling PicoCpuFM68k.not_polling\r
91#define SekNotPollingS68k PicoCpuFS68k.not_polling\r
92\r
b542be46 93#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
5fadfb1c 94#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
b542be46 95\r
cc68a136 96#endif\r
97\r
98#ifdef EMU_M68K\r
99#include "../cpu/musashi/m68kcpu.h"\r
3aa1e148 100extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
cc68a136 101#ifndef SekCyclesLeft\r
ae214f1c 102#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
103#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
3aa1e148 104#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
105#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
12da51c2 106#define SekDar(x) PicoCpuMM68k.dar[x]\r
107#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
108#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
109#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
7a1f6e45 110#define SekSetStop(x) { \\r
3aa1e148 111 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
112 else PicoCpuMM68k.stopped=0; \\r
7a1f6e45 113}\r
114#define SekSetStopS68k(x) { \\r
3aa1e148 115 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
116 else PicoCpuMS68k.stopped=0; \\r
7a1f6e45 117}\r
ed4402a7 118#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
ca61ee42 119#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
08769494 120#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)\r
b542be46 121\r
ecc8036e 122#define SekNotPolling PicoCpuMM68k.not_polling\r
123#define SekNotPollingS68k PicoCpuMS68k.not_polling\r
124\r
71de3cd9 125#define SekInterrupt(irq) { \\r
b542be46 126 void *oldcontext = m68ki_cpu_p; \\r
127 m68k_set_context(&PicoCpuMM68k); \\r
128 m68k_set_irq(irq); \\r
129 m68k_set_context(oldcontext); \\r
130}\r
5fadfb1c 131#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
b542be46 132\r
cc68a136 133#endif\r
ef090115 134#endif // EMU_M68K\r
cc68a136 135\r
ae214f1c 136// while running, cnt represents target of current timeslice\r
137// while not in SekRun(), it's actual cycles done\r
138// (but always use SekCyclesDone() if you need current position)\r
139// cnt may change if timeslice is ended prematurely or extended,\r
140// so we use SekCycleAim for the actual target\r
141extern unsigned int SekCycleCnt;\r
142extern unsigned int SekCycleAim;\r
cc68a136 143\r
ae214f1c 144// number of cycles done (can be checked anywhere)\r
145#define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)\r
146\r
147// burn cycles while not in SekRun() and while in\r
148#define SekCyclesBurn(c) SekCycleCnt += c\r
bc3c13d3 149#define SekCyclesBurnRun(c) { \\r
150 SekCyclesLeft -= c; \\r
b8cbd802 151}\r
cc68a136 152\r
ae214f1c 153// note: sometimes may extend timeslice to delay an irq\r
cc68a136 154#define SekEndRun(after) { \\r
ae214f1c 155 SekCycleCnt -= SekCyclesLeft - (after); \\r
156 SekCyclesLeft = after; \\r
cc68a136 157}\r
158\r
ae214f1c 159extern unsigned int SekCycleCntS68k;\r
160extern unsigned int SekCycleAimS68k;\r
161\r
07ceafdb 162#define SekEndRunS68k(after) { \\r
ae214f1c 163 if (SekCyclesLeftS68k > (after)) { \\r
164 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
165 SekCyclesLeftS68k = after; \\r
166 } \\r
07ceafdb 167}\r
168\r
ae214f1c 169#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
cc68a136 170\r
ae214f1c 171// compare cycles, handling overflows\r
172// check if a > b\r
173#define CYCLES_GT(a, b) \\r
174 ((int)((a) - (b)) > 0)\r
175// check if a >= b\r
176#define CYCLES_GE(a, b) \\r
177 ((int)((a) - (b)) >= 0)\r
cc68a136 178\r
b542be46 179// ----------------------- Z80 CPU -----------------------\r
180\r
b4db550e 181#if defined(_USE_DRZ80)\r
dca310c4 182#include "../cpu/DrZ80/drz80.h"\r
b542be46 183\r
184extern struct DrZ80 drZ80;\r
185\r
186#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
187#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
4936aac1 188#define z80_int() drZ80.Z80_IRQ = 1\r
835122bc 189#define z80_int() drZ80.Z80_IRQ = 1\r
190#define z80_nmi() drZ80.Z80IF |= 8\r
4b9c5888 191\r
192#define z80_cyclesLeft drZ80.cycles\r
19954be1 193#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
b542be46 194\r
195#elif defined(_USE_CZ80)\r
dca310c4 196#include "../cpu/cz80/cz80.h"\r
b542be46 197\r
198#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
199#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
200#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
835122bc 201#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)\r
4b9c5888 202\r
203#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
19954be1 204#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
b542be46 205\r
206#else\r
207\r
208#define z80_run(cycles) (cycles)\r
209#define z80_run_nr(cycles)\r
210#define z80_int()\r
835122bc 211#define z80_nmi()\r
b542be46 212\r
213#endif\r
214\r
b4db550e 215#define Z80_STATE_SIZE 0x60\r
216\r
ae214f1c 217extern unsigned int last_z80_sync;\r
4b9c5888 218extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
219extern int z80_cycle_aim;\r
220extern int z80_scanline;\r
221extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
222\r
223#define z80_resetCycles() \\r
ae214f1c 224 last_z80_sync = SekCyclesDone(); \\r
4b9c5888 225 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
226\r
227#define z80_cyclesDone() \\r
228 (z80_cycle_aim - z80_cyclesLeft)\r
229\r
230#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
231\r
acd35d4c 232// ----------------------- SH2 CPU -----------------------\r
233\r
41397701 234#include "cpu/sh2/sh2.h"\r
acd35d4c 235\r
1d7a28a7 236extern SH2 sh2s[2];\r
237#define msh2 sh2s[0]\r
238#define ssh2 sh2s[1]\r
239\r
679af8a3 240#ifndef DRC_SH2\r
19886062 241# define sh2_end_run(sh2, after_) do { \\r
242 if ((sh2)->icount > (after_)) { \\r
c1931173 243 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
19886062 244 (sh2)->icount = after_; \\r
a8fd6e37 245 } \\r
246} while (0)\r
19886062 247# define sh2_cycles_left(sh2) (sh2)->icount\r
8a847c12 248# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
f81107f5 249# define sh2_pc(sh2) (sh2)->ppc\r
679af8a3 250#else\r
19886062 251# define sh2_end_run(sh2, after_) do { \\r
252 int left_ = (signed int)(sh2)->sr >> 12; \\r
253 if (left_ > (after_)) { \\r
c1931173 254 (sh2)->cycles_timeslice -= left_ - (after_); \\r
f4c0720c 255 (sh2)->sr &= 0xfff; \\r
19886062 256 (sh2)->sr |= (after_) << 12; \\r
a8fd6e37 257 } \\r
258} while (0)\r
19886062 259# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
8a847c12 260# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
f81107f5 261# define sh2_pc(sh2) (sh2)->pc\r
679af8a3 262#endif\r
266c6afa 263\r
19886062 264#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
a7f82a77 265#define sh2_cycles_done_t(sh2) \\r
266 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
19886062 267#define sh2_cycles_done_m68k(sh2) \\r
268 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
269\r
4ea707e1 270#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
271#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
272#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
6add7875 273#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
acd35d4c 274\r
83ff19ec 275#define sh2_set_gbr(c, v) \\r
276 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
277#define sh2_set_vbr(c, v) \\r
278 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
279\r
f8675e28 280#define elprintf_sh2(sh2, w, f, ...) \\r
281 elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
282\r
cc68a136 283// ---------------------------------------------------------\r
284\r
285// main oscillator clock which controls timing\r
286#define OSC_NTSC 53693100\r
b8cbd802 287#define OSC_PAL 53203424\r
cc68a136 288\r
289struct PicoVideo\r
290{\r
291 unsigned char reg[0x20];\r
b8cbd802 292 unsigned int command; // 32-bit Command\r
293 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
294 unsigned char type; // Command type (v/c/vsram read/write)\r
295 unsigned short addr; // Read/Write address\r
296 int status; // Status bits\r
cc68a136 297 unsigned char pending_ints; // pending interrupts: ??VH????\r
b8cbd802 298 signed char lwrite_cnt; // VDP write count during active display line\r
9761a7d0 299 unsigned short v_counter; // V-counter\r
300 unsigned char pad[0x10];\r
cc68a136 301};\r
302\r
303struct PicoMisc\r
304{\r
305 unsigned char rotate;\r
306 unsigned char z80Run;\r
e5503e2f 307 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
2aa27095 308 unsigned short scanline; // 04 0 to 261||311\r
e5503e2f 309 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
310 unsigned char hardware; // 07 Hardware value for country\r
311 unsigned char pal; // 08 1=PAL 0=NTSC\r
45f2f245 312 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
e5503e2f 313 unsigned short z80_bank68k; // 0a\r
be2c4208 314 unsigned short pad0;\r
fa8fb754 315 unsigned char ncart_in; // 0e !cart_in\r
0ace9b9a 316 unsigned char z80_reset; // 0f z80 reset held\r
e5503e2f 317 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
1dceadae 318 unsigned short eeprom_addr; // EEPROM address register\r
45f2f245 319 unsigned char eeprom_cycle; // EEPROM cycle number\r
1dceadae 320 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
45f2f245 321 unsigned char eeprom_status;\r
be2c4208 322 unsigned char pad2;\r
053fd9b4 323 unsigned short dma_xfers; // 18\r
45f2f245 324 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
053fd9b4 325 unsigned int frame_count; // 1c for movies and idle det\r
cc68a136 326};\r
327\r
b4db550e 328struct PicoMS\r
329{\r
330 unsigned char carthw[0x10];\r
331 unsigned char io_ctl;\r
835122bc 332 unsigned char nmi_state;\r
333 unsigned char pad[0x4e];\r
b4db550e 334};\r
335\r
cc68a136 336// some assembly stuff depend on these, do not touch!\r
337struct Pico\r
338{\r
339 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
200772b7 340 union { // vram is byteswapped for easier reads when drawing\r
2ec9bec5 341 unsigned short vram[0x8000]; // 0x10000\r
342 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
343 };\r
cc68a136 344 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
b4db550e 345 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
346 unsigned char pad[0xf0]; // unused\r
cc68a136 347 unsigned short cram[0x40]; // 0x22100\r
348 unsigned short vsram[0x40]; // 0x22180\r
349\r
350 unsigned char *rom; // 0x22200\r
0219d379 351 unsigned int romsize; // 0x22204 (on 32bits)\r
cc68a136 352\r
353 struct PicoMisc m;\r
354 struct PicoVideo video;\r
b4db550e 355 struct PicoMS ms;\r
cc68a136 356};\r
357\r
358// sram\r
45f2f245 359#define SRR_MAPPED (1 << 0)\r
360#define SRR_READONLY (1 << 1)\r
361\r
362#define SRF_ENABLED (1 << 0)\r
363#define SRF_EEPROM (1 << 1)\r
af37bca8 364\r
cc68a136 365struct PicoSRAM\r
366{\r
4ff2d527 367 unsigned char *data; // actual data\r
368 unsigned int start; // start address in 68k address space\r
cc68a136 369 unsigned int end;\r
45f2f245 370 unsigned char flags; // 0c: SRF_*\r
1dceadae 371 unsigned char unused2;\r
cc68a136 372 unsigned char changed;\r
45f2f245 373 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
374 unsigned char unused3;\r
1dceadae 375 unsigned char eeprom_bit_cl; // bit number for cl\r
376 unsigned char eeprom_bit_in; // bit number for in\r
377 unsigned char eeprom_bit_out; // bit number for out\r
45f2f245 378 unsigned int size;\r
cc68a136 379};\r
380\r
381// MCD\r
33be04ca 382#define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)\r
383\r
4f265db7 384struct mcd_pcm\r
385{\r
386 unsigned char control; // reg7\r
387 unsigned char enabled; // reg8\r
388 unsigned char cur_ch;\r
389 unsigned char bank;\r
33be04ca 390 unsigned int update_cycles;\r
4f265db7 391\r
4ff2d527 392 struct pcm_chan // 08, size 0x10\r
4f265db7 393 {\r
394 unsigned char regs[8];\r
4ff2d527 395 unsigned int addr; // .08: played sample address\r
4f265db7 396 int pad;\r
397 } ch[8];\r
398};\r
399\r
4fb43555 400#define PCD_ST_S68K_RST 1\r
401\r
c459aefd 402struct mcd_misc\r
403{\r
6901d0e4 404 unsigned short hint_vector;\r
405 unsigned char busreq; // not s68k_regs[1]\r
406 unsigned char s68k_pend_ints;\r
407 unsigned int state_flags; // 04\r
408 unsigned int stopwatch_base_c;\r
409 unsigned short m68k_poll_a;\r
410 unsigned short m68k_poll_cnt;\r
411 unsigned short s68k_poll_a;\r
412 unsigned short s68k_poll_cnt;\r
413 unsigned int s68k_poll_clk;\r
414 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
415 unsigned char dmna_ret_2m;\r
416 unsigned char need_sync;\r
417 unsigned char pad3;\r
418 int pad4[9];\r
c459aefd 419};\r
420\r
cc68a136 421typedef struct\r
422{\r
3f23709e 423 unsigned char bios[0x20000]; // 000000: 128K\r
424 union { // 020000: 512K\r
425 unsigned char prg_ram[0x80000];\r
426 unsigned char prg_ram_b[4][0x20000];\r
427 };\r
428 union { // 0a0000: 256K\r
429 struct {\r
430 unsigned char word_ram2M[0x40000];\r
431 unsigned char unused0[0x20000];\r
432 };\r
433 struct {\r
434 unsigned char unused1[0x20000];\r
435 unsigned char word_ram1M[2][0x20000];\r
436 };\r
437 };\r
438 union { // 100000: 64K\r
439 unsigned char pcm_ram[0x10000];\r
440 unsigned char pcm_ram_b[0x10][0x1000];\r
441 };\r
f47d0a28 442 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
3f23709e 443 unsigned char bram[0x2000]; // 110200: 8K\r
444 struct mcd_misc m; // 112200: misc\r
445 struct mcd_pcm pcm; // 112240:\r
274fcc35 446 void *cdda_stream;\r
447 int cdda_type;\r
3f23709e 448 int pcm_mixbuf[PCM_MIXBUF_LEN * 2];\r
449 int pcm_mixpos;\r
450 char pcm_mixbuf_dirty;\r
451 char pcm_regs_dirty;\r
cc68a136 452} mcd_state;\r
453\r
be2c4208 454// XXX: this will need to be reworked for cart+cd support.\r
cc68a136 455#define Pico_mcd ((mcd_state *)Pico.rom)\r
456\r
be2c4208 457// 32X\r
acd35d4c 458#define P32XS_FM (1<<15)\r
fa8fb754 459#define P32XS_nCART (1<< 8)\r
83ff19ec 460#define P32XS_REN (1<< 7)\r
461#define P32XS_nRES (1<< 1)\r
462#define P32XS_ADEN (1<< 0)\r
acd35d4c 463#define P32XS2_ADEN (1<< 9)\r
5e128c6d 464#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
4ea707e1 465#define P32XS_68S (1<< 2)\r
97d3f47f 466#define P32XS_DMA (1<< 1)\r
4ea707e1 467#define P32XS_RV (1<< 0)\r
acd35d4c 468\r
5e128c6d 469#define P32XV_nPAL (1<<15) // VDP\r
acd35d4c 470#define P32XV_PRI (1<< 7)\r
4ea707e1 471#define P32XV_Mx (3<< 0) // display mode mask\r
974fdb5b 472\r
e51e5983 473#define P32XV_SFT (1<< 0)\r
474\r
acd35d4c 475#define P32XV_VBLK (1<<15)\r
476#define P32XV_HBLK (1<<14)\r
477#define P32XV_PEN (1<<13)\r
478#define P32XV_nFEN (1<< 1)\r
479#define P32XV_FS (1<< 0)\r
974fdb5b 480\r
df63f1a6 481#define P32XP_RTP (1<<7) // PWM control\r
482#define P32XP_FULL (1<<15) // PWM pulse\r
db1d3564 483#define P32XP_EMPTY (1<<14)\r
484\r
419973a6 485#define P32XF_68KCPOLL (1 << 0)\r
486#define P32XF_68KVPOLL (1 << 1)\r
487#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
4ea707e1 488\r
489#define P32XI_VRES (1 << 14/2) // IRL/2\r
490#define P32XI_VINT (1 << 12/2)\r
491#define P32XI_HINT (1 << 10/2)\r
492#define P32XI_CMD (1 << 8/2)\r
493#define P32XI_PWM (1 << 6/2)\r
494\r
1d7a28a7 495// peripheral reg access\r
496#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
497\r
7eaa3812 498#define DMAC_FIFO_LEN (4*2)\r
db1d3564 499#define PWM_BUFF_LEN 1024 // in one channel samples\r
266c6afa 500\r
f4bb5d6b 501#define SH2_DRCBLK_RAM_SHIFT 1\r
502#define SH2_DRCBLK_DA_SHIFT 1\r
503\r
f81107f5 504#define SH2_READ_SHIFT 25\r
e05b81fc 505#define SH2_WRITE_SHIFT 25\r
506\r
be2c4208 507struct Pico32x\r
508{\r
509 unsigned short regs[0x20];\r
5a681086 510 unsigned short vdp_regs[0x10]; // 0x40\r
511 unsigned short sh2_regs[3]; // 0x60\r
be2c4208 512 unsigned char pending_fb;\r
974fdb5b 513 unsigned char dirty_pal;\r
266c6afa 514 unsigned int emu_flags;\r
4ea707e1 515 unsigned char sh2irq_mask[2];\r
516 unsigned char sh2irqi[2]; // individual\r
517 unsigned int sh2irqs; // common irqs\r
518 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
7eaa3812 519 unsigned int pad[4];\r
df63f1a6 520 unsigned int dmac0_fifo_ptr;\r
4a1fb183 521 unsigned short vdp_fbcr_fake;\r
7eaa3812 522 unsigned short pad2;\r
a8fd6e37 523 unsigned char comm_dirty_68k;\r
524 unsigned char comm_dirty_sh2;\r
df63f1a6 525 unsigned char pwm_irq_cnt;\r
526 unsigned char pad1;\r
a7f82a77 527 unsigned short pwm_p[2]; // pwm pos in fifo\r
528 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
529 unsigned int reserved[6];\r
974fdb5b 530};\r
531\r
532struct Pico32xMem\r
533{\r
534 unsigned char sdram[0x40000];\r
f4bb5d6b 535#ifdef DRC_SH2\r
536 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
537#endif\r
b78efee2 538 unsigned short dram[2][0x20000/2]; // AKA fb\r
b4db550e 539 union {\r
540 unsigned char m68k_rom[0x100];\r
541 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
542 };\r
f4bb5d6b 543#ifdef DRC_SH2\r
544 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
545#endif\r
895d1512 546 union {\r
547 unsigned char b[0x800];\r
548 unsigned short w[0x800/2];\r
549 } sh2_rom_m;\r
550 union {\r
551 unsigned char b[0x400];\r
552 unsigned short w[0x400/2];\r
553 } sh2_rom_s;\r
974fdb5b 554 unsigned short pal[0x100];\r
5e128c6d 555 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
db1d3564 556 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
8ce9c3a7 557 signed short pwm_current[2]; // current converted samples\r
558 unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
be2c4208 559};\r
d49b10c2 560\r
c8d1e9b6 561// area.c\r
fad24893 562extern void (*PicoLoadStateHook)(void);\r
51a902ae 563\r
945c2fdc 564typedef struct {\r
565 int chunk;\r
566 int size;\r
567 void *ptr;\r
568} carthw_state_chunk;\r
569extern carthw_state_chunk *carthw_chunks;\r
570#define CHUNK_CARTHW 64\r
571\r
c8d1e9b6 572// cart.c\r
b4db550e 573extern int PicoCartResize(int newsize);\r
574extern void Byteswap(void *dst, const void *src, int len);\r
45f2f245 575extern void (*PicoCartMemSetup)(void);\r
e807ac75 576extern void (*PicoCartUnloadHook)(void);\r
1dceadae 577\r
c8d1e9b6 578// debug.c\r
b5e5172d 579int CM_compareRun(int cyc, int is_sub);\r
03e4f2a3 580\r
c8d1e9b6 581// draw.c\r
eff55556 582PICO_INTERNAL void PicoFrameStart(void);\r
b6d7ac70 583void PicoDrawSync(int to, int blank_last_line);\r
200772b7 584void BackFill(int reg7, int sh);\r
5a681086 585void FinalizeLine555(int sh, int line);\r
f4750ee0 586extern int (*PicoScanBegin)(unsigned int num);\r
587extern int (*PicoScanEnd)(unsigned int num);\r
b6d7ac70 588extern int DrawScanline;\r
f579f7b8 589#define MAX_LINE_SPRITES 29\r
590extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
5a681086 591extern void *DrawLineDestBase;\r
592extern int DrawLineDestIncrement;\r
cc68a136 593\r
c8d1e9b6 594// draw2.c\r
eff55556 595PICO_INTERNAL void PicoFrameFull();\r
cc68a136 596\r
200772b7 597// mode4.c\r
598void PicoFrameStartMode4(void);\r
599void PicoLineMode4(int line);\r
600void PicoDoHighPal555M4(void);\r
5a681086 601void PicoDrawSetOutputMode4(pdso_t which);\r
200772b7 602\r
c8d1e9b6 603// memory.c\r
eff55556 604PICO_INTERNAL void PicoMemSetup(void);\r
af37bca8 605unsigned int PicoRead8_io(unsigned int a);\r
606unsigned int PicoRead16_io(unsigned int a);\r
607void PicoWrite8_io(unsigned int a, unsigned int d);\r
608void PicoWrite16_io(unsigned int a, unsigned int d);\r
609\r
610// pico/memory.c\r
611PICO_INTERNAL void PicoMemSetupPico(void);\r
cc68a136 612\r
3f23709e 613// cd/cdc.c\r
614void cdc_init(void);\r
615void cdc_reset(void);\r
616int cdc_context_save(unsigned char *state);\r
617int cdc_context_load(unsigned char *state);\r
618int cdc_context_load_old(unsigned char *state);\r
619void cdc_dma_update(void);\r
620int cdc_decoder_update(unsigned char header[4]);\r
621void cdc_reg_w(unsigned char data);\r
622unsigned char cdc_reg_r(void);\r
623unsigned short cdc_host_r(void);\r
624\r
274fcc35 625// cd/cdd.c\r
626void cdd_reset(void);\r
627int cdd_context_save(unsigned char *state);\r
628int cdd_context_load(unsigned char *state);\r
629int cdd_context_load_old(unsigned char *state);\r
630void cdd_read_data(unsigned char *dst);\r
631void cdd_read_audio(unsigned int samples);\r
632void cdd_update(void);\r
633void cdd_process(void);\r
634\r
635// cd/cd_image.c\r
636int load_cd_image(const char *cd_img_name, int *type);\r
637\r
a93a80de 638// cd/gfx.c\r
639void gfx_init(void);\r
640void gfx_start(unsigned int base);\r
641void gfx_update(unsigned int cycles);\r
642int gfx_context_save(unsigned char *state);\r
643int gfx_context_load(const unsigned char *state);\r
644\r
645// cd/gfx_dma.c\r
646void DmaSlowCell(unsigned int source, unsigned int a, int len, unsigned char inc);\r
647\r
c8d1e9b6 648// cd/memory.c\r
eff55556 649PICO_INTERNAL void PicoMemSetupCD(void);\r
fa8fb754 650unsigned int PicoRead8_mcd_io(unsigned int a);\r
651unsigned int PicoRead16_mcd_io(unsigned int a);\r
652void PicoWrite8_mcd_io(unsigned int a, unsigned int d);\r
653void PicoWrite16_mcd_io(unsigned int a, unsigned int d);\r
ae214f1c 654void pcd_state_loaded_mem(void);\r
cc68a136 655\r
c8d1e9b6 656// pico.c\r
cc68a136 657extern struct Pico Pico;\r
658extern struct PicoSRAM SRam;\r
5f9a0d16 659extern int PicoPadInt[2];\r
cc68a136 660extern int emustatus;\r
5e128c6d 661extern int scanlines_total;\r
f8ef8ff7 662extern void (*PicoResetHook)(void);\r
b0677887 663extern void (*PicoLineHook)(void);\r
1e6b5e39 664PICO_INTERNAL int CheckDMA(void);\r
665PICO_INTERNAL void PicoDetectRegion(void);\r
ae214f1c 666PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
cc68a136 667\r
89dbbf2b 668// cd/mcd.c\r
ae214f1c 669#define PCDS_IEN1 (1<<1)\r
670#define PCDS_IEN2 (1<<2)\r
671#define PCDS_IEN3 (1<<3)\r
672#define PCDS_IEN4 (1<<4)\r
673#define PCDS_IEN5 (1<<5)\r
674#define PCDS_IEN6 (1<<6)\r
cc68a136 675\r
2aa27095 676PICO_INTERNAL void PicoInitMCD(void);\r
e5f426aa 677PICO_INTERNAL void PicoExitMCD(void);\r
1cb1584b 678PICO_INTERNAL void PicoPowerMCD(void);\r
2aa27095 679PICO_INTERNAL int PicoResetMCD(void);\r
680PICO_INTERNAL void PicoFrameMCD(void);\r
cc68a136 681\r
ae214f1c 682enum pcd_event {\r
683 PCD_EVENT_CDC,\r
684 PCD_EVENT_TIMER3,\r
685 PCD_EVENT_GFX,\r
686 PCD_EVENT_DMA,\r
687 PCD_EVENT_COUNT,\r
688};\r
689extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
690void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
691void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
a6523294 692void pcd_prepare_frame(void);\r
ae214f1c 693unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
08769494 694int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
fa8fb754 695void pcd_run_cpus(int m68k_cycles);\r
d0132772 696void pcd_soft_reset(void);\r
ae214f1c 697void pcd_state_loaded(void);\r
698\r
33be04ca 699// cd/pcm.c\r
700void pcd_pcm_sync(unsigned int to);\r
701void pcd_pcm_update(int *buffer, int length, int stereo);\r
702void pcd_pcm_write(unsigned int a, unsigned int d);\r
703unsigned int pcd_pcm_read(unsigned int a);\r
704\r
c8d1e9b6 705// pico/pico.c\r
2aa27095 706PICO_INTERNAL void PicoInitPico(void);\r
ed367a3f 707PICO_INTERNAL void PicoReratePico(void);\r
9037e45d 708\r
c8d1e9b6 709// pico/xpcm.c\r
ef4eb506 710PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
711PICO_INTERNAL void PicoPicoPCMReset(void);\r
213c16ad 712PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
ef4eb506 713\r
c8d1e9b6 714// sek.c\r
2aa27095 715PICO_INTERNAL void SekInit(void);\r
716PICO_INTERNAL int SekReset(void);\r
3aa1e148 717PICO_INTERNAL void SekState(int *data);\r
eff55556 718PICO_INTERNAL void SekSetRealTAS(int use_real);\r
b4db550e 719PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
720PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
5f9a0d16 721void SekStepM68k(void);\r
053fd9b4 722void SekInitIdleDet(void);\r
723void SekFinishIdleDet(void);\r
12da51c2 724#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
725void SekTrace(int is_s68k);\r
726#else\r
727#define SekTrace(x)\r
728#endif\r
cc68a136 729\r
c8d1e9b6 730// cd/sek.c\r
2aa27095 731PICO_INTERNAL void SekInitS68k(void);\r
732PICO_INTERNAL int SekResetS68k(void);\r
733PICO_INTERNAL int SekInterruptS68k(int irq);\r
3f23709e 734void SekInterruptClearS68k(int irq);\r
cc68a136 735\r
7a93adeb 736// sound/sound.c\r
c9e1affc 737extern short cdda_out_buffer[2*1152];\r
7a93adeb 738extern int PsndLen_exc_cnt;\r
739extern int PsndLen_exc_add;\r
48dc74f2 740extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
741extern int timer_b_next_oflow, timer_b_step;\r
43e6eaad 742\r
274fcc35 743void cdda_start_play(int lba_base, int lba_offset, int lb_len);\r
744\r
43e6eaad 745void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
d2721b08 746void ym2612_pack_state(void);\r
453d2a6e 747void ym2612_unpack_state(void);\r
4b9c5888 748\r
e53704e6 749#define TIMER_NO_OFLOW 0x70000000\r
45a1ef71 750// tA = 72 * (1024 - NA) / M\r
751#define TIMER_A_TICK_ZCYCLES 17203\r
752// tB = 1152 * (256 - NA) / M\r
753#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
e53704e6 754\r
4b9c5888 755#define timers_cycle() \\r
e53704e6 756 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 757 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
e53704e6 758 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
43e6eaad 759 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
760 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
4b9c5888 761\r
762#define timers_reset() \\r
e53704e6 763 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
48dc74f2 764 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
765 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
43e6eaad 766\r
7a93adeb 767\r
c8d1e9b6 768// videoport.c\r
53f948c9 769extern int line_base_cycles;\r
eff55556 770PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
771PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
9761a7d0 772PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
5de27868 773extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
cc68a136 774\r
c8d1e9b6 775// misc.c\r
bee555ae 776PICO_INTERNAL_ASM void pmemcpy16(unsigned short *dest, unsigned short *src, int count);\r
eff55556 777PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
778PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
779PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
cc68a136 780\r
45f2f245 781// eeprom.c\r
782void EEPROM_write8(unsigned int a, unsigned int d);\r
783void EEPROM_write16(unsigned int d);\r
784unsigned int EEPROM_read(void);\r
785\r
c8d1e9b6 786// z80 functionality wrappers\r
787PICO_INTERNAL void z80_init(void);\r
b4db550e 788PICO_INTERNAL void z80_pack(void *data);\r
789PICO_INTERNAL int z80_unpack(const void *data);\r
c8d1e9b6 790PICO_INTERNAL void z80_reset(void);\r
791PICO_INTERNAL void z80_exit(void);\r
c8d1e9b6 792\r
793// cd/misc.c\r
eff55556 794PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
795PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
796\r
eff55556 797// sound/sound.c\r
9d917eea 798PICO_INTERNAL void PsndReset(void);\r
4b9c5888 799PICO_INTERNAL void PsndDoDAC(int line_to);\r
9d917eea 800PICO_INTERNAL void PsndClear(void);\r
7b3f44c6 801PICO_INTERNAL void PsndGetSamples(int y);\r
2ec9bec5 802PICO_INTERNAL void PsndGetSamplesMS(void);\r
4b9c5888 803extern int PsndDacLine;\r
cc68a136 804\r
3e49ffd0 805// sms.c\r
f3a57b2d 806#ifndef NO_SMS\r
3e49ffd0 807void PicoPowerMS(void);\r
2ec9bec5 808void PicoResetMS(void);\r
3e49ffd0 809void PicoMemSetupMS(void);\r
b4db550e 810void PicoStateLoadedMS(void);\r
3e49ffd0 811void PicoFrameMS(void);\r
87b0845f 812void PicoFrameDrawOnlyMS(void);\r
f3a57b2d 813#else\r
814#define PicoPowerMS()\r
815#define PicoResetMS()\r
816#define PicoMemSetupMS()\r
817#define PicoStateLoadedMS()\r
818#define PicoFrameMS()\r
819#define PicoFrameDrawOnlyMS()\r
820#endif\r
3e49ffd0 821\r
be2c4208 822// 32x/32x.c\r
f3a57b2d 823#ifndef NO_32X\r
be2c4208 824extern struct Pico32x Pico32x;\r
6a98f03e 825enum p32x_event {\r
826 P32X_EVENT_PWM,\r
827 P32X_EVENT_FILLEND,\r
5ac99d9a 828 P32X_EVENT_HINT,\r
6a98f03e 829 P32X_EVENT_COUNT,\r
830};\r
ae214f1c 831extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
6a98f03e 832\r
be2c4208 833void Pico32xInit(void);\r
974fdb5b 834void PicoPower32x(void);\r
be2c4208 835void PicoReset32x(void);\r
974fdb5b 836void Pico32xStartup(void);\r
5e49c3a8 837void PicoUnload32x(void);\r
974fdb5b 838void PicoFrame32x(void);\r
27e26273 839void Pico32xStateLoaded(int is_early);\r
ed4402a7 840void p32x_sync_sh2s(unsigned int m68k_target);\r
19886062 841void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
4d5dfee8 842void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
9e1fa0a6 843void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
844void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
83ff19ec 845void p32x_reset_sh2s(void);\r
19886062 846void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
847void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
5ac99d9a 848void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
a8fd6e37 849\r
be2c4208 850// 32x/memory.c\r
974fdb5b 851struct Pico32xMem *Pico32xMem;\r
be2c4208 852unsigned int PicoRead8_32x(unsigned int a);\r
853unsigned int PicoRead16_32x(unsigned int a);\r
854void PicoWrite8_32x(unsigned int a, unsigned int d);\r
855void PicoWrite16_32x(unsigned int a, unsigned int d);\r
856void PicoMemSetup32x(void);\r
974fdb5b 857void Pico32xSwapDRAM(int b);\r
27e26273 858void Pico32xMemStateLoaded(void);\r
19886062 859void p32x_m68k_poll_event(unsigned int flags);\r
860void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
974fdb5b 861\r
862// 32x/draw.c\r
41946d70 863void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
974fdb5b 864void FinalizeLine32xRGB555(int sh, int line);\r
5a681086 865void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
7a961c19 866void PicoDraw32xLayerMdOnly(int offs, int lines);\r
f4750ee0 867extern int (*PicoScan32xBegin)(unsigned int num);\r
868extern int (*PicoScan32xEnd)(unsigned int num);\r
7a961c19 869enum {\r
870 PDM32X_OFF,\r
871 PDM32X_32X_ONLY,\r
872 PDM32X_BOTH,\r
873};\r
5a681086 874extern int Pico32xDrawMode;\r
be2c4208 875\r
db1d3564 876// 32x/pwm.c\r
c1931173 877unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
878 unsigned int m68k_cycles);\r
879void p32x_pwm_write16(unsigned int a, unsigned int d,\r
880 SH2 *sh2, unsigned int m68k_cycles);\r
db1d3564 881void p32x_pwm_update(int *buf32, int length, int stereo);\r
045a4c52 882void p32x_pwm_ctl_changed(void);\r
df63f1a6 883void p32x_pwm_schedule(unsigned int m68k_now);\r
19886062 884void p32x_pwm_schedule_sh2(SH2 *sh2);\r
9e1fa0a6 885void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
df63f1a6 886void p32x_pwm_irq_event(unsigned int m68k_now);\r
887void p32x_pwm_state_loaded(void);\r
045a4c52 888\r
889// 32x/sh2soc.c\r
890void p32x_dreq0_trigger(void);\r
891void p32x_dreq1_trigger(void);\r
892void p32x_timers_recalc(void);\r
893void p32x_timers_do(unsigned int m68k_slice);\r
cd0ace28 894void sh2_peripheral_reset(SH2 *sh2);\r
f81107f5 895unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
896unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
897unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
8b43bc73 898void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
899void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
900void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
045a4c52 901\r
f3a57b2d 902#else\r
903#define Pico32xInit()\r
904#define PicoPower32x()\r
905#define PicoReset32x()\r
906#define PicoFrame32x()\r
907#define PicoUnload32x()\r
908#define Pico32xStateLoaded()\r
f3a57b2d 909#define FinalizeLine32xRGB555 NULL\r
910#define p32x_pwm_update(...)\r
911#define p32x_timers_recalc()\r
912#endif\r
db1d3564 913\r
45f2f245 914/* avoid dependency on newer glibc */\r
4835077e 915static INLINE int isspace_(int c)\r
45f2f245 916{\r
917 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
918}\r
919\r
f4bb5d6b 920#ifndef ARRAY_SIZE\r
921#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
922#endif\r
923\r
b8cbd802 924// emulation event logging\r
925#ifndef EL_LOGMASK\r
9c9cda8c 926# ifdef __x86_64__ // HACK\r
927# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
928# else\r
1555935b 929# define EL_LOGMASK (EL_STATUS)\r
9c9cda8c 930# endif\r
b8cbd802 931#endif\r
932\r
017512f2 933#define EL_HVCNT 0x00000001 /* hv counter reads */\r
934#define EL_SR 0x00000002 /* SR reads */\r
935#define EL_INTS 0x00000004 /* ints and acks */\r
43e6eaad 936#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
017512f2 937#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
938#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
939#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
940#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
941#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
942#define EL_SRAMIO 0x00000200 /* sram i/o */\r
943#define EL_EEPROM 0x00000400 /* eeprom debug */\r
944#define EL_UIO 0x00000800 /* unmapped i/o */\r
945#define EL_IO 0x00001000 /* all i/o */\r
946#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
947#define EL_SVP 0x00004000 /* SVP stuff */\r
fa22af4c 948#define EL_PICOHW 0x00008000 /* Pico stuff */\r
053fd9b4 949#define EL_IDLE 0x00010000 /* idle loop det. */\r
af37bca8 950#define EL_CDREGS 0x00020000 /* MCD: register access */\r
951#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
be2c4208 952#define EL_32X 0x00080000\r
1b3f5844 953#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
045a4c52 954#define EL_32XP 0x00200000 /* 32X peripherals */\r
ae214f1c 955#define EL_CD 0x00400000 /* MCD */\r
017512f2 956\r
957#define EL_STATUS 0x40000000 /* status messages */\r
958#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
b8cbd802 959\r
960#if EL_LOGMASK\r
961#define elprintf(w,f,...) \\r
a8fd6e37 962do { \\r
b8cbd802 963 if ((w) & EL_LOGMASK) \\r
7d0143a2 964 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
a8fd6e37 965} while (0)\r
dca310c4 966#elif defined(_MSC_VER)\r
967#define elprintf\r
b8cbd802 968#else\r
969#define elprintf(w,f,...)\r
970#endif\r
971\r
f6c49d38 972// profiling\r
973#ifdef PPROF\r
974#include <platform/linux/pprof.h>\r
975#else\r
976#define pprof_init()\r
977#define pprof_finish()\r
978#define pprof_start(x)\r
979#define pprof_end(...)\r
980#define pprof_end_sub(...)\r
981#endif\r
982\r
19886062 983#ifdef EVT_LOG\r
984enum evt {\r
985 EVT_FRAME_START,\r
986 EVT_NEXT_LINE,\r
987 EVT_RUN_START,\r
988 EVT_RUN_END,\r
989 EVT_POLL_START,\r
990 EVT_POLL_END,\r
991 EVT_CNT\r
992};\r
993\r
994enum evt_cpu {\r
995 EVT_M68K,\r
996 EVT_S68K,\r
997 EVT_MSH2,\r
998 EVT_SSH2,\r
999 EVT_CPU_CNT\r
1000};\r
1001\r
1002void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
1003void pevt_dump(void);\r
1004\r
1005#define pevt_log_m68k(e) \\r
08769494 1006 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
19886062 1007#define pevt_log_m68k_o(e) \\r
08769494 1008 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
19886062 1009#define pevt_log_sh2(sh2, e) \\r
1010 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
1011#define pevt_log_sh2_o(sh2, e) \\r
1012 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
1013#else\r
1014#define pevt_log(c, e)\r
1015#define pevt_log_m68k(e)\r
1016#define pevt_log_m68k_o(e)\r
1017#define pevt_log_sh2(sh2, e)\r
1018#define pevt_log_sh2_o(sh2, e)\r
1019#define pevt_dump()\r
1020#endif\r
1021\r
f6c49d38 1022// misc\r
dca310c4 1023#ifdef _MSC_VER\r
1024#define cdprintf\r
1025#else\r
1026#define cdprintf(x...)\r
1027#endif\r
1028\r
8b43bc73 1029#if defined(__GNUC__) && defined(__i386__)\r
553c3eaa 1030#define REGPARM(x) __attribute__((regparm(x)))\r
c8d1e9b6 1031#else\r
553c3eaa 1032#define REGPARM(x)\r
c8d1e9b6 1033#endif\r
1034\r
5e89f0f5 1035#ifdef __GNUC__\r
1036#define NOINLINE __attribute__((noinline))\r
1037#else\r
1038#define NOINLINE\r
1039#endif\r
1040\r
f8af9634 1041#ifdef __cplusplus\r
1042} // End of extern "C"\r
1043#endif\r
1044\r
eff55556 1045#endif // PICO_INTERNAL_INCLUDED\r
1046\r
fast MegaDrive/MegaCD/32X emulator